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Passive CMOS Frequency Divider using Parametric Oscillation

Detailed Technology Description
The first passive CMOS frequency divider has been designed based on the parametric amplification process using a reflective distributed resonator comprised of nonlinear transmission lines.
Others
*Abstract

The first passive CMOS frequency divider has been designed based on the parametric amplification process using a reflective distributed resonator comprised of nonlinear transmission lines. Instead of using active devices, which are the main sources of noise and power consumption in conventional frequency dividers, an oscillation at half of the input frequency is sustained by the parametric process based on nonlinear interaction with the input signal. The input signal injected into the resonator transfers the energy into a divide-by-2 frequency component through degenerate parametric amplification. By traveling back and forth in the resonator, the signal grows and finally achieves the steady state oscillation at a divide-by-2 frequency. The same concept can be used to divide the input frequency by 4 or other numbers.

A proof-of-concept 20 GHz frequency divider has been implemented in a 0.13 µm CMOS process. Without any dc power consumption, 600 mV differential output amplitude is achieved for an input amplitude of 600 mV. The output phase noise is almost 6 dB lower than that of the input signal.

                  

Potential Commercial Applications

Frequency dividers are essential components in phase-locked loops (PLLs) and frequency synthesizers, which are widely used in radio, telecommunications, computers and other electronic applications, for example, in clock distribution networks.

                                

Advantages

  • CMOS compatible implementation
  • No static power consumption and low phase noise
*Licensing
Martin Teschlmt439@cornell.edu(607) 254-4454
Country/Region
USA

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