Zero-Delay Wakeup for Power-Gated Circuits
- Detailed Technology Description
- A new “zero-delay” latency hiding wakeup technique for power gated asynchronous circuits was developed that leverages the robustness of asynchronous circuits to delays and supply voltage variations, and can be used with any of the existing power gating schemes.
- Others
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Issued US patent 9,531,194
Ortega, C.; Tse, J.; Manohar, R.; "Static Power Reduction Techniques for Asynchronous Circuits," 2010 IEEE Symposium on Asynchronous Circuits and Systems (ASYNC), May, 2010
- *Abstract
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A new “zero-delay” latency hiding wakeup technique for power gated asynchronous circuits was developed at Cornell. The technology leverages the robustness of asynchronous circuits to delays and supply voltage variations, and can be used with any of the existing power gating schemes.
Potential Commercial Applications:
- Processors, particularly low power, low duty cycle applications, e.g.:
- Sensor networks
- USB devices
- Digital controls
- Communication systems
Advantages:
- Reduces power leakage in asynchronous circuits
- Zero-delay wakeup of pipeline from sleep mode
- Minimizes voltage fluctuation due to wake-up
- Power gating scheme agnostic
- *Licensing
- Martin Teschlmt439@cornell.edu(607) 254-4454
- Country/Region
- USA
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