Nano-electro-mechanical Non-volatile Memory (nemory)
- Technology Benefits
- Uses standard CMOS materials and processes, scaleable, low voltage levels, high density, three dimensional fabrication
- Technology Application
- Flash memory, storage, RAM
- Detailed Technology Description
- None
- Supplementary Information
- Patent Number: WO2007130919A3
Application Number: WO2007US67812A
Inventor: KAM, Hei | KING, Tsu-Jae
Priority Date: 1 May 2006
Priority Number: WO2007130919A3
Application Date: 30 Apr 2007
Publication Date: 9 Apr 2009
IPC Current: G11C001100 | G11C001150
Assignee Applicant: The Regents of the University of California
Title: NANO-ELECTRO-MECHANICAL MEMORY CELLS AND DEVICES | DISPOSITIFS ET CELLULES MÉMOIRE NANO-ÉLECTROMÉCANIQUES
Usefulness: NANO-ELECTRO-MECHANICAL MEMORY CELLS AND DEVICES | DISPOSITIFS ET CELLULES MÉMOIRE NANO-ÉLECTROMÉCANIQUES
Summary: Used in a mobile consumer electronic such as cellular phone, digital camera, camcorder, personal digital assistant, and moving picture experts group audio layer 3 (MP3) player.
Novelty: Nano-electro-mechanical memory cell e.g. floating-gate and Silicon-Oxide-Nitride-Oxide-Silicon-type memory cell, has mechanical beam provided with portion deflecting toward electrode in response to electrostatic force
- Industry
- Electronics
- Sub Category
- 3C/Gadgets
- Application No.
- 7839710
- Others
-
Tech ID/UC Case
17609/2006-040-0
Related Cases
2006-040-0
- *Abstract
-
By the year 2018, MOSFET gate lengths for logic applications are expected to be scaled below l0nm with operating voltages below 1V. However, flash memory transistors are more difficult to scale because of the thick gate-stack equivalent oxide thickness (EOT) requirements for charge storage (threshold voltage shift) and retention.
Although advanced transistor structures can be leveraged to improve gate-length scalability, high program/erase voltages are still required for fast operation. Thus, alternative integrated-circuit memory technologies such as magnetic RAM (MRAM) and phase-change memory (PCM) have been heavily investigated in recent years. These alternative memory technologies require new materials which increases process complexity and hence cost. In addition, their scalability to sub-10nm cell size is not assured. Therefore, there is a need for a new non-volatile memory technology that can be as scalable (in size and operating voltage) to match the scaling of logic devices.
Researchers at UC Berkeley have developed a new design for nano-scale non-volatile memory. The design fabrication utilizes standard CMOS materials and processes. It leverages established surface micromachining technology and MEMS to achieve an elegantly simple and scalable memory cell structure that can potentially operate with very low voltage levels. The design is ideally suited for use in cross-point memory arrays for very high density non-volatile storage.
- *IP Issue Date
- Nov 23, 2010
- *Principal Investigator
-
Name: Hei Kam
Department:
Name: Tsu Jae King Liu
Department:
- Country/Region
- USA
