A Method For Forming Double-gate Metal Oxide Semiconductor Field Effect Transistors
- Technology Benefits
- double gate structure reduces short channel effectsdouble gates provide enhanced drive current
- Detailed Technology Description
- None
- Supplementary Information
- Patent Number: US6041380A
Application Number: US199810084A
Inventor: LaBerge, Paul A.
Priority Date: 21 Jan 1998
Priority Number: US6041380A
Application Date: 21 Jan 1998
Publication Date: 21 Mar 2000
IPC Current: G06F001340
US Class: 710306 | 710129 | 710105 | 713501
Assignee Applicant: Micron Electronics Inc.,Nampa
Title: Method for increasing the number of devices capable of being operably connected to a host bus
Usefulness: Method for increasing the number of devices capable of being operably connected to a host bus
Summary: Host bus operating method in multi process computer system.
Novelty: Host bus operating method applied in computer system, involves transmitting signal to primary bus after one and half cycles of which address strobe is transmitted to secondary bus
- Industry
- Electronics
- Sub Category
- Semiconductor
- Application No.
- 6413802
- Others
-
Tech ID/UC Case
16952/2000-078-0
Related Cases
2000-078-0
- *Abstract
-
Metal Oxide Semiconductor field effect transistor (MOSFET) technology is the dominant electronic device technology in use today. Performance enhancement is achieved primarily by device scaling. However, as MOSFETs are scaled to channel lengths below 100nm, conventional devices suffer from problems such as short channel effects and reduced gate control. A double gate MOSFET device allows gate control from both sides of the channel and reduces short channel effects. In addition, when the device is turned on using both gates, two conduction layers are formed allowing for increased current flow.
Researchers at the University of California, Berkeley have developed a method for forming double-gate MOSFET and CMOS devices by a fabrication process that is compatible with conventional MOSFET fabrication. The device is fabricated on a silicon layer overlying an insulating layer with the device extending from the insulating layer as a fin. Double gates provide enhanced drive current and effectively suppress short channel effects. Two transistors can be stacked in a fin to provide a CMOS transistor pair having a shared gate.
- *IP Issue Date
- Jul 2, 2002
- *Principal Investigator
-
Name: Jeffrey Bokor
Department:
Name: Leland Chang
Department:
Name: Yang-Kyu Choi
Department:
Name: ChenMing Hu
Department:
Name: Xuejue Huang
Department:
Name: Jakub Kedzierski
Department:
Name: Tsu Jae King Liu
Department:
Name: WEN-CHIN LEE
Department:
Name: Nick Lindert
Department:
Name: Vivek Subramanian
Department:
- Country/Region
- USA
