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Low-Power Synthesis Technique with Dynamic Supply Gating
Summary
Purdue University researchers have developed a novel method to reduce switching power dissipating and subthreshold leakage current in CMOS integrated circuits.
Technology Benefits
Dramatic power reduction without performance sacrificeExtends battery life of portable electronic devices Improves reliability of integrated circuitsIncreased scope of applications for nanometer technologies
Technology Application
CircuitryDevices
Detailed Technology Description
Kaushik RoyNanoelectronics Research LaboratoryPurdue Electrical and Computer Engineering
Countries
United States
Application No.
7,454,738
Country/Region
USA
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