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Low-Power Synthesis Technique with Dynamic Supply Gating
总结
Purdue University researchers have developed a novel method to reduce switching power dissipating and subthreshold leakage current in CMOS integrated circuits.
技术优势
Dramatic power reduction without performance sacrificeExtends battery life of portable electronic devices Improves reliability of integrated circuitsIncreased scope of applications for nanometer technologies
技术应用
CircuitryDevices
详细技术说明
Kaushik RoyNanoelectronics Research LaboratoryPurdue Electrical and Computer Engineering
国家
United States
申请号码
7,454,738
国家/地区
美国
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