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Low-Power Synthesis Technique with Dynamic Supply Gating

Summary
Purdue University researchers have developed a novel method to reduce switching power dissipating and subthreshold leakage current in CMOS integrated circuits.
Technology Benefits
Dramatic power reduction without performance sacrificeExtends battery life of portable electronic devices Improves reliability of integrated circuitsIncreased scope of applications for nanometer technologies
Technology Application
CircuitryDevices
Detailed Technology Description
Kaushik RoyNanoelectronics Research LaboratoryPurdue Electrical and Computer Engineering
Countries
United States
Application No.
7,454,738
*Abstract

*Background
As electronics get smaller, the demand for smaller complementary metal oxide semiconductor (CMOS) devices increases. However, smaller CMOS devices produce undesired effects such as increased subthreshold leakage current. In the past, these problems have been offset by reducing the supply voltage, which results in significant degradation in performance.
*IP Issue Date
Nov 18, 2008
*IP Type
Utility
*Stage of Development
Prototype Testing in Economic Run
*Web Links
Purdue Office of Technology CommercializationPurdueInnovation and EntrepreneurshipKaushik RoyNanoelectronics Research LaboratoryElectrical and Computer Engineering
Country/Region
USA

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