Polymer-Based Heterogeneous Integration Technology
- Summary
- Researchers at Purdue University have developed a new approach to remove the packaging and bulky passive elements from expensive active chips and fabricate them within a less expensive carrier substrate; therefore, reducing the cost of the integrated system.
- Technology Benefits
- Reduces size and costDecreases parasitic capacitance More reliable and efficient
- Technology Application
- MaterialsManufacturingMicroelectronicsNanoelectronics
- Detailed Technology Description
- Saeed MohammadiPurdue Electrical and Computer Engineering
- Countries
- United States
- Application No.
- 7,473,579
- *Abstract
-
- *Background
- One of the most critical levels of electronic packaging is that of packaging and interconnection of integrated circuits and semiconductor devices. Using available technology, there is typically a minimum pitch size for reliable connection between a metallization pad on the chip and the one on the package. This places limitations on the density of interconnections coming out of the chip and introduces additional parasitic capacitance due to the large contact area required. Therefore, driver circuits are often needed to support input/output pads for fast operation.
- *IP Issue Date
- Jan 6, 2009
- *IP Type
- Utility
- *Stage of Development
- Prototype Testing Validated
- *Web Links
- Purdue Office of Technology CommercializationPurdueInnovation and EntrepreneurshipSaeed MohammadiPurdue Electrical and Computer Engineering
- Country/Region
- USA
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