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Improved 3D Transistor

Technology Benefits: Extremely low operating voltage which lowers operating powerAvoids costly and unusual substrate structures common in 2DLeverages conventional techniques to fabricate 3D transistors

Technology Application: Mobile/Portable electronicsData centers and servers

Detailed Technology Description: None

Application No.: 20170162702

Others: Tech ID/UC Case
25614/2016-088-0

Related Cases
2016-088-0

*Abstract: This case helps reinvent the transistor by building on the success of Berkeley’s 3D FinFET/Trigate/Tri-Gate methods and devices, with increased focus on the negative capacitance of the MOS-channel and ferroelectrics, and an unconventional effective oxide thickness approach to the gate dielectric. Proof of concept devices have been demonstrated at 30nm gate length and allow for use of thinner ferroelectric films than 2D negative capacitance transistors (e.g. see http://digitalassets.lib.berkeley.edu/techreports/ucb/text/EECS-2014-226.pdf ). The devices also performed at low operating voltage which lowers operating power.

*IP Issue Date: Jun 8, 2017

*Principal Investigator: Name: ChenMing Hu
Department:

Country/Region: USA

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