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Low-Power Double-Precision Floating-Point Adder and Multiplier

Detailed Technology Description

The first detailed design and implementation of an asynchronous, low-power, double-precision floating-point adder (FPA) and floating point multiplier (FPM) compliant with current standards are presented for vastly improved computing efficiency.

Others

Issued US patent 9,524,270
Sheikh, B.R.; Manohar, R., "An Operand-Optimized Asynchronous IEEE 754 Double-Precision Floating-Point Adder," 2010 IEEE Symposium on Asynchronous Circuits and Systems (ASYNC).
Basit Riaz Sheikh and Rajit Manohar, "An AsynchronousFloating-Point Multiplier," Proceedings of the 18th IEEE InternationalSymposium on Asynchronous Circuits and Systems (ASYNC), May 2012.

Country/Region

USA

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