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Low-Power Double-Precision Floating-Point Adder and Multiplier

詳細技術說明
The first detailed design and implementation of an asynchronous, low-power, double-precision floating-point adder (FPA) and floating point multiplier (FPM) compliant with current standards are presented for vastly improved computing efficiency.
*Abstract

Based on the energy consumption analysis of functional building blocks of a baseline FPA, the energy-efficiency was improved by exploiting data-dependent optimization techniques for each functional block. Circuit simulation of the baseline asynchronous FPA shows a throughput of 2.15 GHz while consuming 69.3 pJ per operation in a 65nm bulk process.

 

A number of micro-architectural and circuit level optimizations are introduced to reduce power consumption in the FPM datapath. The FPM includes a higher radix array multiplier design withoperand-dependent carry propagation adder and low handshake overhead pipelinedesign. It also includes a hardware implementation of denormal andunderflow cases. When compared to a custom synchronous FPM design, thisasynchronous FPM consumes 3X less energy per operation while operating at 2.3Xhigher throughput.

 

Potential Applications:

  • Floating-point arithmetic units for virtually any computer architecture
    • e.g. high performance processors, graphics processing units, etc.

 

Advantages:

  • Fully compliant with IEEE standards
  • Efficiency gains enable improved performance:
    • FPA reduced energy use to less than 50% while retaining throughput with no loss
    • FPM reduced energy use by 33% while increasing throughput over 2X
*Licensing
Martin Teschlmt439@cornell.edu(607) 254-4454
其他
國家/地區
美國

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