System And Method For Testing High-Speed Vlsi Devices Using Slower Testers
The new UC technology provides the key benefit of enabling current testers to test circuits having speeds much higher than their own.This technology available for licensing on a non-exclusive basis.
This new invention has applications in testing high-speed VLSI circuits, particularly where the tester speed is considerably lower than the circuit speed.
Scientists at the University of California have developed a novel method for generating vectors that can be used in a slow tester for testing high-speed VLSI devices and circuits.
Patent Number: US6345373B1
Application Number: US1999296267A
Inventor: Chakradhar, Srimat T. | Krstic, Angela | Cheng, Kwang Ting
Priority Date: 29 Mar 1999
Priority Number: US6345373B1
Application Date: 22 Apr 1999
Publication Date: 5 Feb 2002
IPC Current: G01R0031317 | G01R0031319
US Class: 714738 | 714724
Assignee Applicant: The University of Californianta Barbara | NEC USA. Inc.,Princeton
Title: System and method for testing high speed VLSI devices using slower testers
Usefulness: System and method for testing high speed VLSI devices using slower testers
Summary: For generating vectors to be used in a slow tester for testing VLSI devices.
Novelty: Method of testing high-speed circuits using testers that are slower than high-speed systems such as VLSI by integrating tester speed and model of circuit, applying test vectors at tester speed and observing outputs generated by circuit
Electronics
Circuit Design
6345373
Tech ID/UC Case 10139/1999-298-0 Related Cases 1999-298-0
USA
