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Electric-field-enhanced Photoresist Post-exposure Processing

Technology Benefits

Reduces post-exposure bake time by 30%Improves sharpness of two-dimensional corners and increases verticality of resist sidewallsImproves tolerance of overexposureProvides better critical dimension control

Detailed Technology Description

None

Supplementary Information

Patent Number: US6686132B2
Application Number: US2001840638A
Inventor: Cheng, MoSong | Neureuther, Andrew R.
Priority Date: 20 Apr 2001
Priority Number: US6686132B2
Application Date: 20 Apr 2001
Publication Date: 3 Feb 2004
IPC Current: G03F000738 | G03F0007038 | G03F0007039
US Class: 430325 | 430313
Assignee Applicant: The Regents of the University of California
Title: Method and apparatus for enhancing resist sensitivity and resolution by application of an alternating electric field during post-exposure bake
Usefulness: Method and apparatus for enhancing resist sensitivity and resolution by application of an alternating electric field during post-exposure bake
Summary: For generating resist image on substrate to create patterned material layer structures such as metal wiring lines, holes, insulation section, trenches for capacitor structures used in integrated circuit device fabrication.
Novelty: Resist image generation method for use in integrated circuit devices fabrication, involves subjecting exposed film to postexposure baking while applying alternating electrical field to form latent, patterned image

Industry

Electronics

Sub Group

Circuit Design

Application No.

6686132

Others

Tech ID/UC Case

17062/2001-083-0

Related Cases

2001-083-0

Country/Region

USA

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