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Electric-field-enhanced Photoresist Post-exposure Processing

技術優勢: Reduces post-exposure bake time by 30%Improves sharpness of two-dimensional corners and increases verticality of resist sidewallsImproves tolerance of overexposureProvides better critical dimension control

*Abstract: Researchers at the University of California, Berkeley have developed a methodology for enhancing the resist sensitivity and resolution based on confining the photoacid drift/diffusion by external alternating electric field. Applying the field to the resist film during postexposure bake can enhance the photoacid drift in the vertical direction, reduce the bake time, and thereby confine the lateral acid diffusion.

The researchers have demonstrated a 30% reduction in the post-exposure bake time, along with improvements in the sharpness of the two-dimensional corners and an increase in the verticality of resist sidewalls.

Electric-field-enhanced post exposure bake also significantly improves the tolerance of overexposure and provides better critical dimension control.

*Principal Investigation: Name: Mosong Cheng
Department:

Name: Andrew Neureuther
Department:

附加資料: Patent Number: US6686132B2
Application Number: US2001840638A
Inventor: Cheng, MoSong | Neureuther, Andrew R.
Priority Date: 20 Apr 2001
Priority Number: US6686132B2
Application Date: 20 Apr 2001
Publication Date: 3 Feb 2004
IPC Current: G03F000738 | G03F0007038 | G03F0007039
US Class: 430325 | 430313
Assignee Applicant: The Regents of the University of California
Title: Method and apparatus for enhancing resist sensitivity and resolution by application of an alternating electric field during post-exposure bake
Usefulness: Method and apparatus for enhancing resist sensitivity and resolution by application of an alternating electric field during post-exposure bake
Summary: For generating resist image on substrate to create patterned material layer structures such as metal wiring lines, holes, insulation section, trenches for capacitor structures used in integrated circuit device fabrication.
Novelty: Resist image generation method for use in integrated circuit devices fabrication, involves subjecting exposed film to postexposure baking while applying alternating electrical field to form latent, patterned image

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