A high performance, low noise charge-pump phase-locked loop (PLL)

Lead Inventors: Peter Kinget, Ph.D., Chunwei Hsu, Shih-An Yu, Karthik TripurariProblem or Unmet Need:Phase locked loops (PLLs) are utilized in nearly all modern integrated circuits to provide a number of critical functionalities, such as clock generation, clock recovery, and carrier frequency synthesis. However, the unabated scaling of semiconductor technology has necessitated increasingly high performance integrated PLLs. Current phase detection circuits offer a tradeoff between high dynamic range operation and low in-band phase noise. This technology proposes an innovative PLL design utilizing two complementary phase detection schemes to realize a charge-pump PLL featuring both a large acquisition range and extremely low in-band phase noise. By combining a tri-state digital phase-frequency detector (PFD) with a sub-sampling phase detector, this device can effectively suppress the in-band phase noise characteristic of charge-pump PLLs while maintaining the wide range phase-frequency detection capabilities. This design also obviates the need for an auxiliary loop with a dead zone.

-- Reduces phase noise, resulting in lower signal jitter-- Improves loop bandwidth, offering faster response to rapid signal changes-- Maintains a wide acquisition range -- the range of frequencies that can be synchronized

-- Clock distribution and synchronization in microprocessors and other digital hardware-- Clock recovery in I/O circuits-- Frequency synthesis components for RF communication systems -- i.e. modulators and demodulators

This technology proposes an innovative PLL design utilizing two complementary phase detection schemes to realize a charge-pump PLL featuring both a large acquisition range and extremely low in-band phase noise. By combining a tri-state digital ...

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