Search
  • Within this site
AsiaIPEX is a one-stop-shop for players in the IP industry, facilitating IP trade and connection to the IP world. Whether you are a patent owner interested in selling your IP, or a manufacturer looking to buy technologies to upgrade your operation, you will find the portal a useful resource.
Back to search results

CMOS Negative Resistance/Q Enhancement Method and Apparatus


Summary

Lead Inventors: Nebojsa StanicAn apparatus for optimizing a quality factor Q associated with an electrical resonator system along with an optimizing circuit for providing a negative resistance.The method for optimizing a quality factor and negative resistance comprises of providing a resonator circuit with an inductor and a capacitor. A negative resistance is provided through an optimizing circuit. The optimizing circuit is electrically coupled to the resonator circuit through capacitors. The control voltages applied to the optimizing circuit is adjusted to improve the quality factor Q associated with the resonator circuit.The method provides a negative resistance circuit processing superior linearity characteristics of the circuit.


Detailed Technology Description

An apparatus for optimizing a quality factor Q associated with an electrical resonator system along with an optimizing circuit for providing a negative resistance.The method for optimizing a quality factor and negative resistance comprises of p...


Country/Region

USA

For more information, please click Here
Business of IP Asia Forum
Desktop View