CMOS Negative Resistance/Q Enhancement Method and Apparatus
- 總結
- Lead Inventors: Nebojsa StanicAn apparatus for optimizing a quality factor Q associated with an electrical resonator system along with an optimizing circuit for providing a negative resistance.The method for optimizing a quality factor and negative resistance comprises of providing a resonator circuit with an inductor and a capacitor. A negative resistance is provided through an optimizing circuit. The optimizing circuit is electrically coupled to the resonator circuit through capacitors. The control voltages applied to the optimizing circuit is adjusted to improve the quality factor Q associated with the resonator circuit.The method provides a negative resistance circuit processing superior linearity characteristics of the circuit.
- 詳細技術說明
- An apparatus for optimizing a quality factor Q associated with an electrical resonator system along with an optimizing circuit for providing a negative resistance.The method for optimizing a quality factor and negative resistance comprises of p...
- *Abstract
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None
- *Inquiry
- Calvin Chu Columbia Technology Ventures Tel: (212) 854-8444 Email: TechTransfer@columbia.edu
- *IR
- M04-012
- *Principal Investigation
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- *Web Links
- Patent number: WO2006014692USPTO: US2006017515A1
- 國家/地區
- 美國
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