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Suppression of Defect Formation and Increase in Critical Thickness by Silicon Doping

Technology Benefits
Reduced strain on device layersReduced thread and misfit dislocationsHigh thickness/composition group-III nitride stackingReduced complications of lattice mismatchImproved device performance
Technology Application
UV and Green Region LEDs and LDsGroup-III Nitride MaterialsOptoelectronics and Electronic Devices
Detailed Technology Description
Researchers at the University of California, Santa Barbara have developed a new method to improve performance of group-III nitride devices by limiting the strain-relaxation on crystal substrates to prevent lattice plane slip. This new process uses silicon doping to create a new relaxed buffer layer with limited thread dislocations. This new buffer layer reduces the strain during subsequent growth of III-nitride alloy layers. By reducing this strain on the layers using this process, lattice plane slip is prevented, new thread dislocations are prevented, and overall defect density is reduced allowing for higher performance for ultra-bright LEDs, LDs, and high powered electronic devices.
Supplementary Information
Patent Number: US20120286241A1
Application Number: US13470598A
Inventor: Hardy, Matthew T. | Hsu, Po Shan | DenBaars, Steven P. | SPECK, James S. | Nakamura, Shuji
Priority Date: 13 May 2011
Priority Number: US20120286241A1
Application Date: 14 May 2012
Publication Date: 15 Nov 2012
IPC Current: H01L004900 | H01L002120
US Class: 257014 | 257E2109 | 257E49003 | 438478
Assignee Applicant: The Regents of the University of California
Title: SUPPRESSION OF INCLINED DEFECT FORMATION AND INCREASE IN CRITICAL THICKNESS BY SILICON DOPING ON NON-C-PLANE (Al,Ga,In)N
Usefulness: SUPPRESSION OF INCLINED DEFECT FORMATION AND INCREASE IN CRITICAL THICKNESS BY SILICON DOPING ON NON-C-PLANE (Al,Ga,In)N
Summary: The method is useful for fabricating III-nitride based semiconductor device (claimed), which is useful for fabricating optoelectronic devices (LEDs and laser diodes), electronic devices (a transistor or high electron mobility transistor), or solar cells.
Novelty: Fabricating III-nitride based semiconductor device, useful for e.g. optoelectronic devices (LEDs and laser diodes), comprises growing buffer layer on or above semi-polar or non-polar gallium nitride substrate, and doping the buffer layers
Industry
Environmental/Green Technology
Sub Category
Solar Cell
Application No.
8772758
Others

Background

The usefulness of group-III nitrides such as gallium nitride (GaN) and its alloys has been well established for its use in the fabrication of optoelectronic and high-powered electronic devices. Given recent trends in industry standards, it is desirable to produce ultra-bright LEDs and LDs in the green regions, including colors such as green, amber, and red. The problem with producing LEDs and LDs in the green regions by epitaxy is due to the complications in producing high quality, thick, and high in composition crystals. During growth, the lattice planes of the crystals slip, causing additional threading dislocations which will result in misfit dislocations that degrade the performance of the device.

 


Additional Technologies by these Inventors


Tech ID/UC Case

24138/2011-579-0


Related Cases

2011-579-0
*Abstract
A new method to improve performance of group-III nitride devices by limiting the strain-relaxation on crystal substrates to prevent lattice plane slip.
*IP Issue Date
Jul 8, 2014
*Principal Investigator

Name: Steven DenBaars

Department:


Name: Matthew Hardy

Department:


Name: Po Shan Hsu

Department:


Name: Shuji Nakamura

Department:


Name: James Speck

Department:

Country/Region
USA

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