Current-Mode Clock Distribution

Eliminates the need for complex CM receiver (Rx) circuitry and/or local VM buffers, which reduces power consumption and increases processing on an equivalent silicon area  Use of current mode rather than voltage mode equates to low production cost

System-on-chip architecture

UCSC researchers’ new paradigm for clock distribution uses current, rather than voltage, to distribute a global clock signal with reduced power consumption, making it the first usage in a one-to-many clock distribution network. Inventors created a new high performance current-mode  pulsed flip-flop (CMPFF) which enables 45.2% power reduction on average, when compared to traditional voltage mode clock, and is 60% faster on similar silicon real estate. The invention also eliminates the need for complex CM receiver (Rx) circuitry and local VM buffers as in previously proposed CM signaling schemes.

9787293

Related Technologies

• Distributed Energy Conserving LC Resonant Clock Trees
• High-Performance Clock Grid Synthesis and Tuning Using Distributed LC Resonant Tanks
• Mult-Frequency Resonant Clock Meshes

Additional Technologies by these Inventors

• Distributed Energy Conserving LC Resonant Clock Trees
• High-Performance Clock Grid Synthesis and Tuning Using Distributed LC Resonant Tanks
• Methods for Integrated Circuit C4 Ball Placement Considering Package Reliability
• Mult-Frequency Resonant Clock Meshes

Tech ID/UC Case

23909/2014-341-0

Related Cases

2014-341-0, 2011-195-0, 2011-196-0

USA

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