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CMOS-Compatible Suspended Graphene

Detailed Technology Description

Suspended structures enable control of p-n or n-p-n junctions- the interfaces between diodes, transistors and other semi-conductor devices. However, fabrication of suspended structures using most current techniques is extremely difficult because direct deposition of dielectrics (or ‘insulators’) can stress or even collapse the thin graphene layers employed in these devices. UC researchers have developed a novel technique for fabrication of suspended structures on graphene (Figure 1). The UC technique makes it easier to fabricate a suspended top gate over the semi-conductor substrate and back gate. The top gate makes it easier to apply local electric fields that enhance mobility in graphene p-n and n-p-n junctions.     Figure 1: Suspended          top gate structures on graphene    The UC technique offers the following advantages relative to existing techniques: It is compatible with large-scale CMOS technology It utilizes air or vacuum as the dielectric rather than solid materials. This eliminates current leakage, a recurring problem in most currently fabricated CMOS devices Ease of deposition of suspended top gate eliminates unintentional damage to graphene Fabrication in only one vacuum cycle vastly reduces manufacturing costs   The UC technique ensures that the graphene devices formed do not suffer from undesirable defects that arise from deposition of intervening layers that involve introduction of impurities and dopants. The technique does not require etching of sacrificial (or ‘resist’) layers, which may inadvertently edge other components during fabrication.   The new UC technique can also be applied to fabrication of other types of devices that are highly sensitive to process-induced damage. These devices may include sensors for detection of local magnetic fields and micro-electrochemical (MEM) devices with moving parts such as resonators.   The UC technique can also be used to induce local magnetic fields, which can be employed in conjunction with magnetic media for data storage. The localization of magnetic fields eliminates the need for a read/write head that moves over the surface of the magnetic media. The use of high density array of suspended structures using the UC technique may result in production of high density magnetic storage devices.

Supplementary Information

Patent Number: US7948042B2
Application Number: US2009397183A
Inventor: Lau, Chun Ning | Liu, Gang | Velasco, Jr., Jairo
Priority Date: 3 Mar 2008
Priority Number: US7948042B2
Application Date: 3 Mar 2009
Publication Date: 24 May 2011
IPC Current: H01L002984
US Class: 257415 | 257417 | 257419 | 257E27005 | 257E27046 | 257E27064 | 257E43002 | 257E43003 | 257E43007
Assignee Applicant: The Regents of the University of California
Title: Suspended structures
Usefulness: Suspended structures
Summary: Suspended structure i.e. top gate structure, for use in a graphene device i.e. graphene p-n-p junction device, as a local current carrying wire for inducing a local magnetic field in a magnetic storage device (claimed). Can also be used for a point contact for local injection of current, and moving part in microelectromechanical device.
Novelty: Suspended structure i.e. top gate structure, for use in graphene device, has graphene layer on surface of substrate, and dielectric e.g. vacuum, interposed between electrically conductive suspended structure and graphene layer

Industry

Electronics

Sub Category

Semiconductor

Application No.

7948042

Others

Tech ID/UC Case

19560/2008-481-2

Related Cases

2008-481-2

*Abstract

None

*IP Issue Date

May 24, 2011

*Principal Investigator

Name: Chun Ning Jeani Lau

Department:

Name: Gang Liu

Department:

Name: Jairo Velasco, Jr.

Department:

Country/Region

USA