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Improved Dram With Capacitorless Double-gate

Technology Benefits

Can be scaled below 100 nmReduces Vt fluctuations between different cells due to process variationsAllows for low voltage operationAllows fast sensingProvides small off-state leakageProvides excellent disturb behaviorCan be constructed in a compact 4F2 cell sizeCan be extended to 3-D integrationCan be fabricated with conventional materials that are commonly used in CMOS processes

Technology Application

DG-DRAM exhibits characteristics that suggest its use in stand-alone and embedded sub-100 nm DRAM applications.

Detailed Technology Description

None

Supplementary Information

Patent Number: US7710771B2
Application Number: US2007890674A
Inventor: Kuo, Charles C. | Liu, Tsu-Jae King
Priority Date: 20 Nov 2002
Priority Number: US7710771B2
Application Date: 7 Aug 2007
Publication Date: 4 May 2010
IPC Current: G11C001134
US Class: 365184 | 36518502 | 36518518 | 36518524 | 36518525 | 36518528
Assignee Applicant: The Regents of the University of California
Title: Method and apparatus for capacitorless double-gate storage
Usefulness: Method and apparatus for capacitorless double-gate storage
Summary: Electronic memory circuit operating method for operating memory circuit in electronic devices such as mobile phone, portable computers, and personal digital assistant (PDA).
Novelty: Electronic memory circuit operating method for operating memory circuit in e.g. mobile phone, involves determining value stored on memory circuit using drain current measured by detecting number of charge carriers at back interface

Industry

Electronics

Sub Group

3C/Gadgets

Application No.

7710771

Others

Related Materials

A Capacitorless Double-Gate DRAM Cell; Charles Kuo, Tsu-Jae King, Senior Member, IEEE, and Chenming Hu, Fellow, IEEE; IEEE ELECTRON DEVICE LETTERS

Tech ID/UC Case

17172/2002-079-0

Related Cases

2002-079-0

Country/Region

USA

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