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Quantum Computing Circuits

IP Title

Quantum Computing Circuits

Detailed Technology Description

None

Supplementary Information

Inventor: Wu, Cheng-Hsiao | Cain, Casey Andrew
Priority Number: US8525544B2
IPC Current: H03K0019195
US Class: 326005 | 326006
Assignee Applicant: The Curators of the University of Missourilumbia
Title: Quantum computing circuits
Usefulness: Quantum computing circuits
Novelty: Method for performing digital operations using quantum computing circuit, involves reading state of irreducibly-coupled AB ring network, and evaluating state read by what portion transmission probability can be measured on terminals

Industry

Electronics

Sub Category

Circuit Design

Application Date

Sep 4, 2012

Application No.

8,525,544

Others

*Abstract

The electron transport through Aharonov-Bohm (AB) rings with external terminals has been well studied and experimentally verified in 1985. The inventive paradigm for computing uses single and irreducibly-coupled AB rings with multiple external terminals to perform digital logic operations. The inputs to the circuit are phase coherent directional magnetic fluxes which correspond to persistent currents of a given spin direction, while the outputs are a classically measurable current wave. This spin up/spin down relationship is analogous to spintronic-based quantum computing, but the inventive technology is a much easier extension from the current transistor-based lithographic techniques in terms of assembly. Spintronic has coherence issues that will be difficult to overcome in constructing real-world circuits that are capable of performing Boolean algebraic operations. The invention demonstrates a half-adder circuit with two coupled AB rings, something that normally takes up to 16 traditional CMOS transistors in classical computing to achieve.The inventive quantum networks are governed by a set of scaling laws which show transmission and device operation to work identically from the mesoscopic region all the way down to atomic-size rings. All other emerging technologies have major scalability issues especially when going into the single-nanometer and below range. By being able to scale as small as fabrication techniques allow, it is possible to create much more dense and powerful integrated logic circuits based upon the inventive scheme.

*IP Issue Date

Sep 3, 2013

*IP Publication Date

Mar 7, 2013

*Principal Investigator

Name: Cheng Hsiao Wu, PROFESSOR

Department:

Name: Casey Cain, GRA - ECE

Department:

Country/Region

USA