A Method of Data-Driven Adder for Higher Performance, Lower Power & Energy Saving. (Bar Ilan)

Chip power reduction has become extremely important recently especially in the fields of cellular phones. This invention involves the design of the adder for simplification of circuit design and subsequent power reduction.

This invention makes the operation of an adder being dependent on the augend and addend. Unlike ordinary adders which operate similarly for all numbers, the proposed adder examines the addend and augend in parallel to the addition operation being performed. The adder then decides whether the result obtained is valid or whether further time is required to complete the addition for a valid result. This approach allows designing an adder for the average (mean) carry worst-case rather than for the worst-case carry, which is the entire bit count, as usually done in adder hardware design. The adder then signals the system whether or the sum obtained will be valid after the clock cycle is completed.

With a proper design of the adder, the probability of proper sum can be made very close to one. In case of invalid sum notification, the system (e.g. pipeline) must take care of it, e.g., by allocating more cycles.

The design of such an adder simplifies the circuits involved in its implementation, making the adder operate faster while consuming far less power and energy.

Patent pending

Initial calculations and design analysis have been completed.

Israel