Complementary Metal-Oxide-Semiconductor Transistor Structure for High Density and High Performance Integrated Circuits 一種用于高集成度、高性能集成電路的互補型金屬氧化物半導體晶體管結構
- Summary
- Three-dimensional integrated circuit (IC) is considered to be one of the most promising method for implementing future high density and performance IC applications. However, setting up a satisfying IC device is still a very challenging technically under current technology. Problems include challenges with building high quality of single crystallized silicon, thermal budget restriction as well as scaling limitations.
This invention can provide new and useful methods and apparatus for the fabrication of three dimensional IC with high density and high performance. In general terms, the present invention proposes a stacked fin-CMOS device structure, meaning building a multi-layer fin on an insulating layer. With the use of this invention, high density three-dimensional technology can be built with significantly shortened wiring distance, based on ultra-scaled devices and high quality material. Simple fabrication method is used and the technology is compatible with standard planar IC manufacturing process.
This structure is novel, unique and manufacturable with the ease of processing compared to current technologies. With its super short channel device property, high density and good heat dissipation 3D structure and the low manufacturing cost, this invention is capable of overcoming the disadvantages of the IC devices found in the market.
- Technology Benefits
- 1. Easy process for realizing 3-D technology
2. Super short channel device property
3. High density and good heat dissipate 3-D structure
4. Lower manufacturing cost due to standard process
- Technology Application
- - Modern ULSI applications for high denisty and high performance
- IC design
- Supplementary Information
- Patent Number: US7154500B2
Application Number: US2004829022A
Inventor: Heng, Pheng Ann | Xie, Yongming | Wong, Tien Tsin | Chui, Yim Pan
Priority Date: 20 Apr 2004
Priority Number: US7154500B2
Application Date: 20 Apr 2004
Publication Date: 26 Dec 2006
IPC Current: G06T001504 | G06T001540 | G06T001700 | G09G000500
US Class: 345424
Assignee Applicant: The Chinese University of Hong Kong
Title: Block-based fragment filtration with feasible multi-GPU acceleration for real-time volume rendering on conventional personal computer
Usefulness: Block-based fragment filtration with feasible multi-GPU acceleration for real-time volume rendering on conventional personal computer
Summary: Used for interactive volume rendering of amounts of volume data in form of a stack of original two dimensional slices into displayable images on a display of a personal computer.
Novelty: Interactive volume rendering method for use in personal computer, involves applying block-based fragment filtration to processed blocks to obtain image units suited for display and render final image
- Industry
- Electronics
- Sub Category
- Semiconductor
- Application Date
- 3 Feb 2006
- Application No.
- US 11/347164
- Patent Information
- US 7545008
- ID No.
- TTC.PA.245
- Country/Region
- Hong Kong
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