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Vsat Structure for Nonvolatile Memory Device

Detailed Technology Description

None

Supplementary Information

Patent Number: US8164134B2
Application Number: US2009481403A
Inventor: Kim, Ji-Young | Wang, Kang L. | Park, Yong-Jik | Han, Jeong-Hee | Hong, Augustin Jinwoo
Priority Date: 9 Jun 2009
Priority Number: US8164134B2
Application Date: 9 Jun 2009
Publication Date: 24 Apr 2012
IPC Current: H01L0029792 | H01L0027108
US Class: 257314 | 257328 | 257329 | 257330 | 257397
Assignee Applicant: Samsung Electronics Co. Ltd.
Title: Semiconductor device
Usefulness: Semiconductor device
Summary: Semiconductor device e.g. memory card of flash memory system used in data processing system such as mobile apparatus and desk computer.
Novelty: Semiconductor device e.g. memory card of flash memory system, has semiconductor pattern that comprises horizontal portion arranged between gate lines, connects upper and lower interconnection

Industry

Electronics

Sub Category

Semiconductor

Application No.

8164134

Others

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• Vertical Gate-Depleted Single Electron Transistors
• Novel Telegraph Signal Microscope For Visualizing Single Atoms And Detecting Defects In Nanotechnology Devices
• Novel Nanomaterial-based Thermo-Photovoltaic Cells
• Graphene Flash Memory Device
• Vertical-Stacked-Array-Transistor (VSAT) for Nonvolatile Memory Devices
• Epitaxial Growth of Single Crystalline MgO on Germanium
• A Self-Organized Critical CMOS Circuit for Computation and Information Processing
• Anti-Ferromagnetic Magneto-Electric Spin-Orbit Read Logic
• Quasi Van Der Walls Epitaxy Of GaAs on Graphene
• Periodically Rippled Antenna
• Graphene-Polymer Nanocomposite Incorporating Chemically Doped Graphene-Polymer Heterostructure for Flexible and Transparent Conductive Films
• Fabrication Of 1D Sinusoidal Silicon Dioxide Substrate
• Strained Voltage-Controlled Magnetic Memory Elements and Devices

Tech ID/UC Case

22317/2009-453-0

Related Cases

2009-453-0

*Abstract

Provided are a semiconductor device and a method of fabricating the same. At least one mold structure defining at least one first opening is formed on a substrate, wherein the mold structure comprises first mold patterns and second mold patterns that are sequentially and alternatingly stacked. Thereafter, side surfaces of the first mold patterns are selectively etched to form undercut regions between the second mold patterns. Then, a semiconductor layer is formed to cover a surface of the mold structure where the undercut regions are formed, and gate patterns are formed, which fill respective undercut regions where the semiconductor layer is formed.

*IP Issue Date

Apr 24, 2012

*Principal Investigator

Name: Jeong-hee Han

Department:

Name: Augustin Hong

Department:

Name: Ji Young Kim

Department:

Name: Yong-Jik Park

Department:

Name: Kang Wang

Department:

Country/Region

USA