Circuits, Architectures and CAD Algorithms for Power Efficient FPGAs
Reduced Power Consumption (50% Reduction Observed)Extremely Low Utilization RateCompatible with Traditional FPGA LayoutDoes Not Overly Complicate the CAD Flow
Digital Signal ProcessingImage ProcessingAerospace & DefenseCommunication SystemsMedical ImagingCryptography
Researchers at UCLA have developed a simple and effective FPGA design methodology for low-power applications. Through selectively applying a lower power supply to unused logic blocks and interconnects, the proposed method reduces the total power consumption, without requiring complicated power-reduction blocks.
Patent Number: US7714610B2
Application Number: US2006566573A
Inventor: He, Lei
Priority Date: 4 Jun 2004
Priority Number: US7714610B2
Application Date: 4 Dec 2006
Publication Date: 11 May 2010
IPC Current: H03K0019177 | G06F001750
US Class: 326041 | 326038 | 326039 | 326040
Assignee Applicant: The Regents of the University of California
Title: Low-power FPGA circuits and methods
Usefulness: Low-power FPGA circuits and methods
Summary: Field programmable gate array (FPGA) circuit.
Novelty: Field programmable gate array circuit includes selection unit that selects supply voltage from multiple discrete supply voltage levels, for operating logic blocks and switching elements within programmable routing channels
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7714610
State Of Development Background Related Materials Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics, F. Li, Y. Lin, L. He, J. Cong, International Symposium on Field Programmable Gate Arrays, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays table of contents (2004) Additional Technologies by these Inventors Tech ID/UC Case 21688/2004-645-0 Related Cases 2004-645-0
FPGA power reduction using configurable dual-Vdd, F. Li, Y. Lin, L. He, Annual ACM IEEE Design Automation Conference, Proceedings of the 41st annual Design Automation Conference (2004)
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