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Circuits, Architectures and CAD Algorithms for Power Efficient FPGAs

技术优势

Reduced Power Consumption (50% Reduction Observed)Extremely Low Utilization RateCompatible with Traditional FPGA LayoutDoes Not Overly Complicate the CAD Flow

技术应用

Digital Signal ProcessingImage ProcessingAerospace & DefenseCommunication SystemsMedical ImagingCryptography

详细技术说明

Researchers at UCLA have developed a simple and effective FPGA design methodology for low-power applications. Through selectively applying a lower power supply to unused logic blocks and interconnects, the proposed method reduces the total power consumption, without requiring complicated power-reduction blocks.

*Abstract

Researchers at UCLA have developed a FPGA design that significantly reduces power consumption while remaining compatible with conventional FPGA designs.

*Applications

• Digital Signal Processing
• Image Processing
• Aerospace & Defense
• Communication Systems
• Medical Imaging
• Cryptography

*IP Issue Date

May 11, 2010

*Principal Investigation

Name: Lei He

Department:

附加资料

Patent Number: US7714610B2
Application Number: US2006566573A
Inventor: He, Lei
Priority Date: 4 Jun 2004
Priority Number: US7714610B2
Application Date: 4 Dec 2006
Publication Date: 11 May 2010
IPC Current: H03K0019177 | G06F001750
US Class: 326041 | 326038 | 326039 | 326040
Assignee Applicant: The Regents of the University of California
Title: Low-power FPGA circuits and methods
Usefulness: Low-power FPGA circuits and methods
Summary: Field programmable gate array (FPGA) circuit.
Novelty: Field programmable gate array circuit includes selection unit that selects supply voltage from multiple discrete supply voltage levels, for operating logic blocks and switching elements within programmable routing channels

主要类别

电子

细分类别

电路设计

申请号码

7714610

其他

State Of Development

Circuit simulation shows potential power reduction of 2x to 5x compared to existing FPGA chips without Vdd programmability

Background

While FPGAs are attractive design platforms due to their low cost and short time to market, their power efficiencies are much lower than that of traditional ASIC designs. Currently, many of the power optimization techniques proposed to overcome this problem significantly complicate the design and do not address all sources of power consumption.

Related Materials

Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics, F. Li, Y. Lin, L. He, J. Cong, International Symposium on Field Programmable Gate Arrays, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays table of contents (2004)

FPGA power reduction using configurable dual-Vdd, F. Li, Y. Lin, L. He, Annual ACM IEEE Design Automation Conference, Proceedings of the 41st annual Design Automation Conference (2004)

Additional Technologies by these Inventors

• FPGA Device and Architecture Evaluation Considering Process Variations
• In-Place Reconfiguration for Programmable Logic

Tech ID/UC Case

21688/2004-645-0

Related Cases

2004-645-0

国家/地区

美国