Vertical Gate-Depleted Single Electron Transistors
ADVANTAGES: The new UC technology provides the following benefits: Easier to interconnect than present devices; Increased integration density and improved performance; Allows for gate-splitting architectures; Simplifies the fabrication process.
Scientists at the University of California have developed a novel approach to fabricating these devices which greatly simplifies the process while allowing the gate to be split into multiple gates.
Patent Number: US7547932B2
Application Number: US2002302635A
Inventor: Zhang, Yaohui | Baron, Filipp A. | Wang, Kang L.
Priority Date: 22 Nov 2002
Priority Number: US7547932B2
Application Date: 22 Nov 2002
Publication Date: 16 Jun 2009
IPC Current: H01L0027108 | H01L002976 | H01L0029812
US Class: 257281 | 257192 | 257263 | 257280 | 257623
Assignee Applicant: The Regents of the University of California
Title: Vertical gate-depleted single electron transistor
Usefulness: Vertical gate-depleted single electron transistor
Summary: In semiconductor industry for reducing the device sizes.
Novelty: Vertical gate-depleted single electron transistor device in semiconductors industry comprises a mesa and gate Schottky contacts on top of interleaved layers of basic material and tunneling barrier with the mesa having ohmic contact
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7547932
BACKGROUND Additional Technologies by these Inventors Tech ID/UC Case 10257/2002-421-0 Related Cases 2002-421-0
In current vertical gate-depleted single electron transistors, the mesa must be etched to the point just below the tunneling barrier. In addition, the gate Schottky contact must wrap the pillar containing the tunneling barriers. These requirements considerably complicate the processing of these devices.
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