A DRAM-initiated Retention Management Scheme
ΓÇó Handles up to 10% weak row population with negligible performance and energy overhead.ΓÇó Can be built atop any modern DRAM architecture
Background:Dynamic Random Access Memory (DRAM) has been the main computer memory technology for decades because it successfully strikes a balance between performance and cost. A DRAM cell consists of one transistor and one capacitor. The capacitor can be either charged or discharged to represent a binary value (e.g. 0 or 1). This scheme provides a high degree of integration making DRAM the cheapest memory solution, but capacitors leak charge over time, and stored data eventually fades unless DRAM cell is periodically refreshed. As a result, in modern computer systems, memory refresh operations are needed so that the charge on the capacitor can be restored to its original level. This degrades system performance and consumes additional energy. With DRAM scaling towards sub-20nm process technology, a significant portion of DRAM cells become weak cells and require a higher refresh rate, resulting in even higher refresh overhead. Invention Description:This new technology allows DRAM to proactively guide the timing of weak cell refresh management and reuses the memory controllersΓÇÖ capability in command scheduling to send out auxiliary row activation commands. Through this sideband channel, it is able to run retention-aware refresh management on a row granularity while still utilizing DRAMΓÇÖs auto-refresh feature. This smart retention-aware refresh on the DRAM row granularity can be built atop any modern DRAM architecture. It can handle up to 10% weak row population with negligible performance and energy overhead. This technology has been demonstrated through computer simulation.
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