Low-Power Booth-Encoded Carry-Save Array Multiplier
The new UC technology provides the following benefits: Reduces power dissipation by 18% when the Booth-encoded input has a small magnitude; Does not dissipate extra power when the Booth-encoded input is a random signal; Does not require extra circuits or additional routing overhead; Does not require extra circuit delay.
This new UC invention is useful in digital integrated circuit (IC) design for digital signal processing applications.
Scientists at the University of California have developed a novel "reorganized" but regular partial-product addition scheme that demonstrates all of the advantages of the traditional carry-save array while reducing power dissipation.
Patent Number: US7225217B2
Application Number: US2002268602A
Inventor: Willson, Jr., Alan N. | Yu, Zhan | Wasserman, Larry S.
Priority Date: 9 Oct 2001
Priority Number: US7225217B2
Application Date: 9 Oct 2002
Publication Date: 29 May 2007
IPC Current: G06F000752 | G06F0007533
US Class: 708630
Assignee Applicant: The Regents of the University of California
Title: Low-power Booth-encoded array multiplier
Usefulness: Low-power Booth-encoded array multiplier
Summary: Used in digital signal processing applications.
Novelty: Array multiplier for digital signal processing application, has generator to produce partial products that are added in increasing sequence of transition probabilities with most significant digital product in adder array
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7225217
BACKGROUND Multipliers for digital signal processing (DSP) applications widely use the well-known modified Booth-encoding algorithm due to its ability to reduce the number of partial products. As the interconnect power dissipation begins to dominate in deep sub-micron designs, the regular structure of the carry-save array makes it the preferred method for partial-product reduction. Tech ID/UC Case 10245/2002-055-0 Related Cases 2002-055-0
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