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Enhanced Patterning Of Integrated Circuits

技术优势

One additional step rather than manySelf-aligns to pre-existing surface featuresProduces features smaller than the current resolution limitDoubles the density of featuresFinal feature sizes can be fine-tuned

技术应用

Producing ICs with complex patternsProducing ICs with increased feature density

详细技术说明

None

申请号码

20180130668

其他

Additional Technologies by these Inventors

Two-Dimensional Patterning Of Integrated Circuit Layer By Tilted Ion Implantation

Tech ID/UC Case

24717/2015-085-0

Related Cases

2015-085-0

国家/地区

美国

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