Enhanced Patterning Of Integrated Circuits
- 技術優勢
- One additional step rather than manySelf-aligns to pre-existing surface featuresProduces features smaller than the current resolution limitDoubles the density of featuresFinal feature sizes can be fine-tuned
- 技術應用
- Producing ICs with complex patternsProducing ICs with increased feature density
- 詳細技術說明
- None
- *Abstract
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Information and communication technologies rely on integrated circuits (ICs) or “chips.” Increased integration has improved system performance and energy efficiency, and lowered the manufacturing cost per component. Moore’s Law predicts that the number of transistors on an IC will double every two years, yet industry experts predict that we are reaching economic limits of traditional circuit patterning processes.
Photolithographic patterning is best suited to print linear features that are evenly spaced. The smaller or more complex the shape, the more likely the printed pattern will be blurred and unusable. Although multiple-patterning techniques can be used to increase feature density on ICs, they bring a high additional cost to the process. This means that the most advanced ICs available today have a high density of features, but are restricted to having simple patterns and are increasingly expensive to produce. Without innovations in production techniques, Moore’s Law will reach its end in the near future.
To address this issue, researchers at UC Berkeley have developed a one-step method to increase feature density on chips. This method is capable of achieving arbitrarily small feature size, and self-aligns to pre-existing features on the surface formed by other techniques.
- *IP Issue Date
- May 10, 2018
- *Principal Investigation
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Name: Tsu-Jae King Liu
Department:
Name: Xi Zhang
Department:
Name: Peng Zheng
Department:
- 申請號碼
- 20180130668
- 其他
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Additional Technologies by these Inventors
Tech ID/UC Case
24717/2015-085-0
Related Cases
2015-085-0
- 國家/地區
- 美國
