Picoihc- High Bandwidth Integrate- and- Hold Circuits
A new approach to achieve the function of sample and hold (S/H) for analog digital converter (ADC), it improves the bandwidth of the ADC with simple circuit topology.
Very high bandwidth
Tunable bandwidth
Extremely short delay times possible
Simple layout
Prototype available
This novel IHC topology enables extremely short delays independent from the minimum delay times of the utilized delay elements.
Two shunted switches (herein multipliers) both receive the input signal. A differential amplifier subtracts the outputs of both switches and delivers the difference to the input of the resettable integrator. Two tunable delay elements feed track command inputs of both switches, wherein both delay element inputs receive the inverted integrate command.
The integration time is the difference between the delay times delay1 and delay2. The unique characteristic of the novel circuit is, that the delay difference can be adjusted to much shorter delays and with a considerably higher resolution than a single delay.
This novel IHC topology enables
Licensing
28/02/2018 00:00:00
DE102018104546A1
- international:
H03M1/12
- cooperative:
H03M1/1245 (EP); H03M1/1215 (EP)
Patent application
5197
Germany
