Electromigration on Signal Interconnects

Efficiently Characterizes Cell-internal ElectromigrationThe problem of cell-internal electromigration (EM) on signal interconnects within a standard cell is solved using this technology which efficiently characterizes EM characteristics of gates in a standard cell library, under all pin positions, based on a single circuit simulation and graph-based methods. The approach uses Joule heating effects to model and efficiently characterize cell-internal EM to analyze the lifetime of large benchmark circuits. A related method optimizes circuit lifetime by changing pin positions in gates within a circuit. This procedure has demonstrated an approximate 60% increase in circuit lifetime.Optimization of Circuit LifetimeStandard cell-based gate libraries are the bedrock of integrated circuit design. Electromigration (EM) in on-chip metal interconnects is a critical reliability failure mechanism in nanometer-scale technologies and is an increasing problem in integrated circuits that reduces circuit lifetime. Traditionally, EM affected global wires, but in current and future technologies, within-gate wires will also be significantly affected. Currently, EM checks in existing technologies are performed ad hoc; no current methods systematically perform cell-internal EM or allocate pin positions to increase the lifetime of a circuit that uses numerous standard cells. This technology provides a systematic and computationally efficient way for analyzing cell-level EM and translating it to an analysis and optimization of circuit level lifetimes.BENEFITS AND FEATURES:Models and efficiently characterizes cell-internal EMCharacterizes EM characteristics of gates in a standard cell library under all pin positionsAnalyzes lifetime of large benchmark circuitsOptimizes circuit lifetimeJoule heating effectsSolves cell-internal EM problemsApproximate 60% increase in circuit lifetimeAPPLICATIONS:Integrated circuit designCircuit designPhase of Development - Prototype dev

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