Methods To Detect And Respond To Trojan IC Attacks
Dynamic, real-time algorithmCompatible with traditional designsImmune to various types of Trojan attacks
Integrated Circuits (IC) System-On-Chip (SoC)Communication systemsComputer systemsConsumer electronicsDefense systems
Researchers at UCLA have developed a novel set of countermeasures that can be incorporated into integrated circuits to identify and stop Trojan attacks. The method stops attacks that occur without any advanced warning, in a chip that was incorrectly believed to be free of any hidden malicious circuitry. Through implementing a secure SoC bus architecture that is compatible with traditional designs, the system is successfully protected against real-time Trojan attacks, without incurring high costs in terms of bus resources and performances.
Patent Number: US8549630B2
Application Number: US13042233A
Inventor: Villasenor, John D | Kim, Lok Won
Priority Date: 5 Mar 2010
Priority Number: US8549630B2
Application Date: 7 Mar 2011
Publication Date: 1 Oct 2013
IPC Current: G06F001214 | G06K000504
US Class: 726022 | 714699
Assignee Applicant: The Regents of the University of California
Title: Trojan-resistant bus architecture and methods
Usefulness: Trojan-resistant bus architecture and methods
Novelty: Method for protecting system-on-chip bus architecture from trojan attack during manufacturing integrated circuit, involves securing bus matrix by activating malicious wait detection signal by comparator
Electronics
Computer System
8549630
Background Related Materials "A Trojan Resistant System-On-Chip Bus Architecture," Proc. IEEE MILCOM. Conf. October 2009. Tech ID/UC Case 21585/2010-586-0 Related Cases 2010-586-0
USA

