An All Solid-State Wafer Bonding Method Of III-V Materials On Si CMOS Using Patterned Metal Structures
This invention enables the integration of high-mobility III-V transistor layers, such as InGaAs, atop Si CMOS circuits. It also enables the integration of the high-speed optoelectronic elements made from InP (waveguides, modulators, switches and photodetectors) that are necessary for optical transmission with large data rate and bandwidth atop a Si CMOS circuit. This has a huge potential market for big data centers and on-chip optical processing in microprocessor chips. Further, light emission (Lasers, light emitting diodes) and detection (photodetectors, photoconductors, photovoltaic cells) made of III-V materials can be integrated with this invention on Si CMOS.
Electrical engineers from UC San Diego have developed a novel wafer bonding method for integrating bulk or thin film functional semiconductor materials (III-V compounds) to a rigid host substrate (e.g. Si wafer). Specifically, this invention exploits a solid-state reaction between the functional semiconductor layer and a metal layer that is pre-deposited and optionally pre-patterned on the rigid host substrate, a low temperature heat treatment (< 250 C), and a fast bonding process. This novel wafer bonding process reduces the critical requirements of extremely low surface roughness (< 0.5 nm) for both the functional semiconductors and the host substrate, enables multiple layers of functional semiconductors for bonding to the host substrate with precise locations, and provides the platform to fabricate advanced electronic and optoelectronic devices utilizing the transferred functional semiconductors on Si, all in a CMOS compatible fabrication process. This technology also teaches the novel conceptual design of “Self-aligned Electrical Contacts (SAEC)”, in which the pre-patterned electrical metal contacts on the host substrate play the roles of bonding with functional semiconductors and also as conductive electrical leads to the outer electrodes. To summarize, this patent-pending technology demonstrates the first prototype for integrating III-V (or other functional semiconductor) materials onto rigid host substrate (for example Si) by a solid-state reaction between the III-V semiconductor and the metal layer pre-defined on the host substrate. Invention provides a number of advantages over existing methods, including:(1) Tolerance to surface imperfections.(2) Compatibility to Si CMOS process.(3) Integration to a variety of substrates.(4) Possibility of multi-layer stacking.(5)“Self-aligned electrical contacts (SAEC)” for III-V transistors on Si. This method may lead the way to very short-channel high-performance devices.
20170317050
State Of Development Inventors have demonstrated the feasibility of manufacturing methods for bonding III-V semiconductor materials to a rigid host substrate by utilizing metal-semiconductor solid-state reactions. Both bulk (InP) and thin film (InGaAs) III-V semiconductors have been successfully bonded to Si wafer with SiO2 dielectric layer with metal stripes atop in the lab as completion with the current invention. The experimental results demonstrate the feasibility of the novel wafer bonding technology and the novel SAEC process for advanced functional device fabrication in a CMOS compatible process for potential active III-V devices on top of CMOS circuitry. Tech ID/UC Case 24761/2015-074-0 Related Cases 2015-074-0
USA
