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FPGA Hardware Compiler

Technology Benefits

Auto-generates "calling" interface circuitry that procides arbitraion between function invocation points Enables proper and efficient use of C functions according to standard language syntax and semantics, including calling by reference (pointers to functions), separate compilation, "object code" libraries, etc. Allows mainstream system software developers to design algorithms and applications that can be efficiently synthesised on FPGAs

Detailed Technology Description

Current hardware design practices are inappropriate for the enormous gate-counts of today's FPGAs. To deal with the increasing complexity. hardware design needs to become more like software development. High level synthesis (HLS) raises the level of design abstraction for FPGAs and leverages some of the advantages offered by modern software development techniques. HLS offers the potential to shorten design cycles, reduce non-recurrent costs and accelerate speed to market. However, there are a number of significant limitations in the current generation of HLS tools. One limitation in particularly - the handling of function calls - is stifling the adoption of HLS for FPGA design. This problem is most acute in the fields of high-performance and re-configurable computing using FPGA-based platforms. New FPGA hardware compiler code-generation technology will enable full and proper implementation of function calls for high-level FPGA designs and algorithms written in the C programming language, avoiding the need for subroutine circuitry to be duplicated or 'inlined' at each calling point. In addition, calls to functions can be resolved at 'link time', enabling separate compilation of subroutines and libraries. This breakthrough will enable third party code to be licensed and distributed in object code format, driving the market for development and licensing of IP blocks. The new compiler technology also supports the 'call by reference' model, allowing the address of a function to be passed as an argument to another function. This mechanism provides enhanced flexibility in program design and enables efficient implementation of certain HPC algorithms, such as parallel MapReduce frameworks.

Supplementary Information

Inventor: WILLIAMS, Ambrose | DENG, Wenbin
Priority Number: WO2012112458A3
IPC Current: C12N001563 | A61K003512 | C12N000510 | C12N001586
Assignee Applicant: The Regents of the University of California
Title: COMPOSITIONS AND METHODS FOR INCREASING REPROGRAMMING EFFICIENCY | COMPOSITIONS ET PROCÉDÉS D'ACCROISSEMENT DE L'EFFICACITÉ DE REPROGRAMMATION
Usefulness: COMPOSITIONS AND METHODS FOR INCREASING REPROGRAMMING EFFICIENCY | COMPOSITIONS ET PROCÉDÉS D'ACCROISSEMENT DE L'EFFICACITÉ DE REPROGRAMMATION
Summary: The method is useful for enhancing the efficiency of reprogramming a non-pluripotent cell to a pluripotent cell. The cell or population of cells are useful for screening a cell with a variation of a gene of interest for an agent to treat a disease or disorder and for determining disease mechanisms in a condition, which affects molecular pathway of interest, where the molecular pathway is a disease-associated pathway (all claimed). No biological data given.
Novelty: Enhancing efficiency of reprogramming non-pluripotent cell to pluripotent cell, comprises expressing pluripotency factors in cell and overexpressing poly(adenosine diphosphate-ribose)polymerase 1 or its equivalent or polynucleotide

Industry

Biomedical

Sub Group

DNA/Gene Engineering

Country/Region

USA

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