Layout Optimization for Time-dependent Dielectric Breakdown Reliability in VLSI
- 技術應用
- At a 32nm foundry node this layout optimization technique increases chip-level lifetime by 9% to 10%. At a 20nm process and below, the effect will be even more substantial. This improved chip lifetime also means that chips can be operated at a higher supply voltage for a given lifetime if TDDB is the primary limiting factor affecting the allowable supply voltage for a given layout. Further impacts on chip layout such as printability and electromigration should also experience positive improvements.
- 詳細技術說明
- Given here is a new post-layout optimization approach to mitigate dielectric breakdown and provide design correction prior to manufacture. Experimental results demonstrate an improved interconnect lifetime of as much as 10% following application of this optimization technique. Applying a second signal-aware chip-level TDDB reliability estimation using the stress time of interconnects based on net signals, the chip-level TDDB lifetime is approximately double that obtained by conventional analysis in which interconnects are always assumed to be under electrical stress.
- *Abstract
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Time-dependent dielectric breakdown (TDDB) is becoming a critical reliability issue in VLSI design, since the electric field across dielectrics barriers increases as technology scales downward. Moreover, dielectric reliability is aggravated when interconnect spacings vary due to misalignment between via and wire masks. Although dielectric reliability can be mitigated by a larger interconnect pitch, such a guardband leads to significant area overhead.
- *IP Issue Date
- Mar 20, 2018
- *Principal Investigation
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Name: Tuck Boon Chan
Department:
Name: Andrew Kahng
Department:
- 申請號碼
- 9922161
- 其他
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Related Materials
Tech ID/UC Case
23223/2013-213-0
Related Cases
2013-213-0
- 國家/地區
- 美國
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