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GaN-based Vertical Metal Oxide Semiconductor and Junction Field Effect Transistors

Technology Benefits

·         Reduced chip cost due to small chip size ·         Improved device performance over any current GaN-based transistors on the market ·         High switching speed and extremely low contact resistance and drift resistance

Technology Application

·         Metal oxide semiconductor field effect transistors (MOSFETs) ·         Junction gate field effect transistors (JFETs)

Detailed Technology Description

Researchers have designed the first true vertical GaN-based transistors, where gating is also performed on electrons traveling perpendicular to the surface in a vertical channel. Drift region spreading resistance is extremely low, and is achieved by inserting a two-dimensional electron gas produced at a heterojunction within the device on either side of the channel. This method significantly improves the device performance because it utilizes the full area of the drift region for conduction. The gating of the device is variable, allowing for the creation of a metal oxide semiconductor field effect transistor (MOSFET) or a junction gate field effect transistor (JFET). In addition, to reduce resistance and chip cost, the electrically active area of the device can be equal to the geometric chip area.

Application No.

20170125574

Others

Background

In recent years, GaN-based transistors have attracted much attention because of their high-power performance. The effectiveness of lateral GaN on silicon-based high electron mobility transistors (HEMTs) has been demonstrated through their commercial availability. However, these devices are fairly complex and expensive to fabricate, and have a large device area. One method to alleviate some of these issues is to replace lateral GaN transistors with vertical GaN-based transistors. 

Additional Technologies by these Inventors

• Novel Current-Blocking Layer in High-Power Current Aperture Vertical Electron Transistors (CAVETs)
• (In,Ga,Al)N Optoelectronic Devices with Thicker Active Layers for Improved Performance
• Polarization-Doped Field Effect Transistors with Increased Performance
• High-Quality N-Face GaN, InN, AlN by MOCVD
• Defect Reduction in GaN films using in-situ SiNx Nanomask
• Improved Fabrication of Nonpolar InGaN Thin Films, Heterostructures, and Devices
• Technique for the Nitride Growth of Semipolar Thin Films, Heterostructures, and Semiconductor Devices
• A Structure For Increasing Mobility In A High-Electron-Mobility Transistor
• III-N Based Material Structures and Circuit Modules Based on Strain Management
• Achieving “Active P-Type Layer/Layers” In III-Nitride Epitaxial Or Device Structures Having Buried P-Type Layers
• Improved Performance of III-Nitride Photonic Devices
• Gated Electrodes For Electrolysis And Electrosynthesis
• Fabrication of N-face to Improve Telecommunications Efficiency
• Methods for Locally Changing the Electric Field Distribution in Electron Devices

Tech ID/UC Case

24820/2014-718-0

Related Cases

2014-718-0

*Abstract

The first true vertical GaN-based transistors, where gating is also performed on electrons traveling perpendicular to the surface in a vertical channel.

*IP Issue Date

May 4, 2017

*Principal Investigator

Name: Srabanti Chowdhury

Department:

Name: Stacia Keller

Department:

Name: Umesh Mishra

Department:

Name: Chirag Gupta

Department:

Name: Jeonghee Kim

Department:

Name: Silvia Chan

Department:

Country/Region

USA