Hybrid Network-On-Chip Design with RF Interconnects for Chip Multiprocessors (CMPs)
- Technology Benefits
- Use of RF-I overcomes limitations of traditional repeated RC wire communications Enables high bandwidth, low latency, and low energy consumption Application-specific reconfiguration of NoC designs
- Technology Application
- Global interconnects for network-on-chip(NoC) communications Chip multi-processor (CMP) communications On-chip and off-chip communications
- Detailed Technology Description
- Researchers at UCLA have demonstrated that hybridizing RF interconnects (RF-I) into RC wire based network-on-chip (NoC) designs for chip multi-processors (CMPs) allows significant acceleration of communication, decreased power consumption, and great amount of flexibility for compile-time or runtime reconfiguration of NoC topology for communication optimization.
- Supplementary Information
- Patent Number: US8270316B1
Application Number: US2009363182A
Inventor: Chang, Mau-Chung F. | Cong, Jason | Kaplan, Adam | Naik, Mishali | Reinman, Glenn | Socher, Eran | Tam, Sai-Wang | Liu, Chunyue
Priority Date: 30 Jan 2009
Priority Number: US8270316B1
Application Date: 30 Jan 2009
Publication Date: 18 Sep 2012
IPC Current: H04L001228
US Class: 370254 | 370352 | 370389 | 370392 | 370410 | 710052 | 710061 | 710116 | 710243
Assignee Applicant: The Regents of the University of California
Title: On-chip radio frequency (RF) interconnects for network-on-chip designs
Usefulness: On-chip radio frequency (RF) interconnects for network-on-chip designs
Novelty: Integrated circuit e.g. monolithic integrated circuit, for use in complementary metal-oxide-semiconductor device, has radio frequency receiver demodulates radio frequency modulated signal to recover data for circuit node
- Industry
- ICT/Telecom
- Sub Category
- Telecommunication
- Application No.
- 8270316
- Others
-
State of Development
Plans to implement a RF-I NoC prototype chip.
Background
The continued scaling of CMOS devices and the transition to multiple processing cores increases the amount of on-chip interconnects that are required for inter-core communications. Repeated RC wires or RC wire based NoC provide current on-chip communications. However, the RC wires scale poorly and result in increased latency and power consumption.
Related Materials
M. Chang, J. Cong, A. Kaplan, M. Naik, G. Reinman, E. Socher and S.W. Tam, CMP Network-on-Chip Overlaid With Multi-Band RF-Interconnect, The 14th International Symposium on High-Performance Computer Architecture, Salt Lake City, UT, February 2008 - [more]
M.-C. F. Chang, E. Socher, S.-W. Tam, J. Cong, and G. Reinman, RF Interconnects for Communications On-chip, Proceedings of the 2008 ACM International Symposium on Physical Design, Portland, Oregon, pp. 78-83, April 2008 - [more]Additional Technologies by these Inventors
- Wire Width Planning for VLSI Interconnect Performance Optimization
- Improved Programmable Logic Circuit Architecture Using Resistive Memory Elements
- Trainable Filter Emulator For Real-Time Control Systems
Tech ID/UC Case
20053/2008-716-0
Related Cases
2008-716-0
- *Abstract
-
Scientists at UCLA in the Computer Science and Electrical Engineering Departments have designed a hybrid network of RF interconnects and traditional mesh architectures for advanced network-on-chip (NoC) communications for chip multiprocessors.
- *IP Issue Date
- Sep 18, 2012
- *Principal Investigator
-
Name: Mau-Chung Frank Chang
Department:
Name: Jingsheng Cong
Department:
Name: Adam Kaplan
Department:
Name: Chunyue Liu
Department:
Name: Mishali Naik
Department:
Name: Glenn Reinman
Department:
Name: Eran Socher
Department:
Name: Sai Wang Tam
Department:
- Country/Region
- USA
