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Bit Serial Digital Winner Take All Circuit
總結
Researchers at Purdue University have developed a new Winner Take All circuit structure which is a fully parallel bit-serial digital WTA. It can identify the largest among a large number of m-bit data in m-cycles. The time taken by the circuit to identify the maximum among the inputs is independent of the number of inputs, which leads to fast and low power WTA operation.
技術優勢
Faster operation time that is independent of the number of inputsLow power requirement
技術應用
WTA circuit
詳細技術說明
Kaushik RoyNanoelectronics Research LaboratoryPurdue Electrical and Computer Engineering
國家
United States
申請號碼
9489618
國家/地區
美國
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