Bit Serial Digital Winner Take All Circuit
- 总结
- Researchers at Purdue University have developed a new Winner Take All circuit structure which is a fully parallel bit-serial digital WTA. It can identify the largest among a large number of m-bit data in m-cycles. The time taken by the circuit to identify the maximum among the inputs is independent of the number of inputs, which leads to fast and low power WTA operation.
- 技术优势
- Faster operation time that is independent of the number of inputsLow power requirement
- 技术应用
- WTA circuit
- 详细技术说明
- Kaushik RoyNanoelectronics Research LaboratoryPurdue Electrical and Computer Engineering
- *Abstract
-
- *Background
- Winner Take All (WTA) is a computational principle applied in computational models of neural networks. WTA is used to identify the maximum among a large number of m-bit input values. It is a critical part of pattern matching applications to find the maximum among the outputs of a distance-evaluation matrix. Current WTA circuits are based on a binary tree structure. In these circuits, the number of stages and nodes in the binary WTA tree increases when the number of inputs to the WTA increases, leading to a larger delay and area.
- *IP Issue Date
- Nov 8, 2016
- *IP Type
- Utility
- *Stage of Development
- Prototype testing
- *Web Links
- Purdue Office of Technology CommercializationPurdueInnovation and EntrepreneurshipKaushik RoyNanoelectronics Research LaboratoryElectrical and Computer Engineering
- 国家
- United States
- 申请号码
- 9489618
- 国家/地区
- 美国
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