Two-Dimensional topology for faster, more robust on-chip interconnection networks
- 总结
- Dominique Deserable, Ph.D.
- 技术优势
- Increased connectivity, making it more fault-tolerant than the existing 2D torus.Shorter paths between cores, which decreases computing time. Ultimately, this leads to more computing power in a more robust network. An easy-to-implement routing algorithm mathematically proven to find the shortest paths.
- 技术应用
- Parallel computing in supercomputersArchitecture for telecommunications networksMulticore system processing in embedded systemsMulticore system processing in mobile devicesMulticore system processing in personal computers and tabletsScalable parallel IP address lookup architecture using algorithm of 2D torus
- 详细技术说明
- Dominique Deserable, Ph.D.
- *Abstract
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None
- *Inquiry
- Teresa FazioColumbia Technology VenturesTel: (212) 854-8444Email: TechTransfer@columbia.edu
- *IR
- CU13220
- *Principal Investigation
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- *Publications
- Deserable, Dominique. “A family of Cayley graphs on the hexavalent grid.” Discrete applied mathematics 93.2 (1999): 169-189.Tech Ventures Reference: IR CU13220
- 国家/地区
- 美国
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