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Taper Matrix Based Edge Coupler for Standard Single Mode Fiber

Summary: Researchers at Purdue University have developed a multilayer format edge coupler for SMF-28® fiber where mode is coupled to silicon via an intermediate layer as a stepping stone. This intermediate layer requires less taper length for the coupling performance, making application more efficient with this layer. In addition, a silicon nitride tip array or matrix can be deployed at the facet to capture input mode, which allows the mode to be tailored to maximize overlap. A thicker buried oxide layer can reduce the leakage toward the Si substrate. While transverse electric (TE) modes suffer less leakage, the transverse magnetic (TM) modes suffer less transition and scattering loss. However, with this technology, a taper can be designed with distinct features from both TE and TM sections, optimizing performance.

Technology Benefits: Intermediate layer Silicon nitride Both TE and TM features

Technology Application: Edge couplingIndustrial solution

Detailed Technology Description: Minghao QuiPurdue Electrical and Computer EngineeringMURI Project

Countries: United States

Application No.: None

*Abstract: None

*Background: Silicon (Si) inverse nanotapers are promising as fiber-to-chip edge couplers due to the perceived advantages of broadband performance and the ease of on-chip integration. The Lipson Nanophotonics Group at Columbia University developed the earliest Si inverse taper, where a Si taper is embedded in silicon dioxide (SiO2). However, conventional inverse taper does not suit standard cleaved fiber SMF-28® with mode field diameter (MFD) around 10 micrometers due to lack of thickness. Many techniques have been established to account for this disparity such as reducing leakage via a lensed fiber beam or deploying a taper fiber core to achieve mode size reduction. Unfortunately, both techniques have not yet become well-accepted industry solutions due to higher costs and significantly increased alignment challenges.

*IP Issue Date: None

*IP Type: Utility

*Stage of Development: Prototype Testing in Economic Run

*Web Links: Purdue Office of Technology CommercializationPurdue Innovation and EntrepreneurshipMinghao QuiPurdue Electrical and Computer EngineeringMURI Project

Country/Region: USA

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