Current-Mode Clock Distribution
- Technology Benefits
- Eliminates the need for complex CM receiver (Rx) circuitry and/or local VM buffers, which reduces power consumption and increases processing on an equivalent silicon area Use of current mode rather than voltage mode equates to low production cost
- Technology Application
- System-on-chip architecture
- Detailed Technology Description
- UCSC researchers’ new paradigm for clock distribution uses current, rather than voltage, to distribute a global clock signal with reduced power consumption, making it the first usage in a one-to-many clock distribution network. Inventors created a new high performance current-mode pulsed flip-flop (CMPFF) which enables 45.2% power reduction on average, when compared to traditional voltage mode clock, and is 60% faster on similar silicon real estate. The invention also eliminates the need for complex CM receiver (Rx) circuitry and local VM buffers as in previously proposed CM signaling schemes.
- Application No.
- 9787293
- Others
-
Related Technologies
- Distributed Energy Conserving LC Resonant Clock Trees
- High-Performance Clock Grid Synthesis and Tuning Using Distributed LC Resonant Tanks
- Mult-Frequency Resonant Clock Meshes
Additional Technologies by these Inventors
- Distributed Energy Conserving LC Resonant Clock Trees
- High-Performance Clock Grid Synthesis and Tuning Using Distributed LC Resonant Tanks
- Methods for Integrated Circuit C4 Ball Placement Considering Package Reliability
- Mult-Frequency Resonant Clock Meshes
Tech ID/UC Case
23909/2014-341-0
Related Cases
2014-341-0, 2011-195-0, 2011-196-0
- *Abstract
-
Portable electronic devices require long battery lifetimes to meet the longer use times. This can only be obtained by utilizing low-power components, which have become quite critical in system-on-chips (SOCs) because interconnections found in scaled technologies is consuming an increasingly significant amount of power. Researchers have demonstrated that the major consumers of this power are global buses, clock distribution networks (CDNs), and synchronous signals in general.
In addition to power, interconnect delay poses a major obstacle to high-frequency operation. Technology scaling reduces transistor and local interconnect delay while increasing global interconnect delay. Moreover, conventional CDN structures are becoming increasingly difficult for multi-GHz ICs because skew, jitter, and variability are often proportional to large latencies.
Prior to to and in early CMOS technologies, current-mode (CM) logic was the attractive high speed signaling scheme because they were used for long global wires or, more commonly, off chip signals. Standard logic signals, however, have remained in voltage mode (VM) to benefit from low static power of CMOS logic. Researchers at University of California, Santa Cruz, have proposed a scheme that utilizes the power and reliability of CM signaling, yet retain compatibility with low-power CMOS logic.
- *IP Issue Date
- Oct 10, 2017
- *Principal Investigator
-
Name: Matthew Guthaus
Department:
Name: Riadul Islam
Department:
- Country/Region
- USA
