Optimized Vertical Power DMOSFETS in Silicon Carbide
- Summary
- Researchers at Purdue University have developed a structure and method of fabrication of a vertical DMOSFET in silicon carbide that achieves minimum on-state resistance and maximum breakdown voltage.
- Technology Benefits
- Increases breakdown voltage without increasing internal resistivityProvides consistent internal resistance at a greater operating temperature range
- Technology Application
- MaterialsManufacturing
- Detailed Technology Description
- James Cooper Jr.Purdue Electrical and Computer Engineering
- Countries
- United States
- Application No.
- 7,498,633
- *Abstract
-
- *Background
- An important feature in a vertical double-diffused metal oxide semiconductor field effect transistor (DMOSFET) is its ability to drive a load with minimal parasitic resistance at a given breakdown voltage. When the load is switched off, the maximum breakdown voltage is crucial. A DMOSFET produced using silicon carbide process material will have higher breakdown voltage than a DMOSFET produced in other process materials but often will have a higher parasitic resistance.
- *IP Issue Date
- Mar 3, 2009
- *IP Type
- Utility
- *Stage of Development
- Prototype Testing
- *Web Links
- Purdue Office of Technology CommercializationPurdueInnovation and EntrepreneurshipJames Cooper Jr.Purdue Electrical and Computer Engineering
- Country/Region
- USA
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