Self-synchronized RF Interconnect for 3-dimensional Circuit Integration

Requires less power than alternative methods. AC coupling eliminates DC power consumption Cost and complexity of production are reduced. Complex etching is unnecessary since AC coupling scheme does not require via etching. A high-speed interconnect with improved signal integrity.

Researchers at UCLA have developed an innovative method to transmit and receive signals between active device layers. The technology is called a Self-Synchronized RF-Interconnect (SSRFI). The active device layers are connected through an AC coupling methodology. By removing the need for etching interconnect vias, the 3D IC fabrication process cost is reduced and yields are improved. This novel method outperforms other RF connects that require additional overhead circuitry. The result is reduced design complexity, power consumption, chip area, and improved signal integrity.

Patent Number: US8131250B2
Application Number: US2006356770A
Inventor: Gu, Qun | Xu, Zhiwei | Ko, Jenwei | Chang, Mau Chung Frank
Priority Date: 18 Feb 2005
Priority Number: US8131250B2
Application Date: 17 Feb 2006
Publication Date: 6 Mar 2012
IPC Current: H04B000128
US Class: 455333 | 257071 | 257135 | 257277 | 257278 | 438074 | 455073 | 4555501
Assignee Applicant: The Regents of the University of California
Title: Self-synchronized radio frequency interconnect for three-dimensional circuit integration
Usefulness: Self-synchronized radio frequency interconnect for three-dimensional circuit integration
Summary: Used for a wireline data communication system.
Novelty: Wireline data communication for three dimensional circuit integration, has self-synchronized radio frequency interconnect circuit vertically interconnecting components in integrated circuit that includes coupling capacitors

信息和通信技術/電信

電信

8131250

State of Development

UCLA researchers have developed and tested a prototype SSFRI chip in UMC 0.18um CMOS technology.

Background

The demand for higher performance, lower power and lower cost semiconductor chips, has driven new methods for chip design. Due to physical constraints, the current planar integrated circuit technology is not able to handle all of these demands. Three-dimensional integrated circuits (3D ICs) design technologies mitigate current physical constraints, but continue to pose manufacturing/cost challenges.Current methods for connecting vertical active device layers in 3D ICs involves etching which is complex, costly, and interferes with circuit performance. Alternative techniques involving RF interconnects have significant power consumption and design overhead. An efficient vertical interconnection is a key technology to realize future 3D ICs.

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Tech ID/UC Case

20178/2005-018-0

Related Cases

2005-018-0

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