Direct Patterning of Silicon by Photoelectrochemical Etching
A wide variety of fields, such as sensors, microfluidics, microanalysis, MEMS, and cell biology might benefit from this invention.
Researchers at UC San Diego have invented a resistless projection lithographic method to generate three-dimensional patterns on silicon substrates. A porous silicon layer is formed first by projecting an image or test pattern onto a silicon substrate during standard electrochemical etching. The porous layer is then removed in a wet etch revealing a 3-D image or test pattern in micrometer resolution. This technique does not involve the use of complicated, multi-step lithography or mask aligners. It is also quick; a multilayered master can be made from a computer design in less than 60 minutes. Feature sizes of 70 microns have been demonstrated, but smaller features should be possible.
Patent Number: US7433811B2
Application Number: US2004838859A
Inventor: Gao, Jun | Sailor, Michael J. | Bhatia, Sangeeta | Flaim, Christopher
Priority Date: 6 May 2003
Priority Number: US7433811B2
Application Date: 4 May 2004
Publication Date: 7 Oct 2008
IPC Current: G06F001750 | B81C000100 | C25F000312 | C25F000314 | H01L002126 | H01L00213063 | C23C002000
US Class: 703012 | 205067 | 257E21216 | 716050 | 716021
Assignee Applicant: The Regents of the University of California
Title: Direct patterning of silicon by photoelectrochemical etching
Usefulness: Direct patterning of silicon by photoelectrochemical etching
Summary: For generating three-dimensional pattern for use in soft lithography.
Novelty: Generation of three-dimensional pattern by immersing substrate and second electrical conductor into hydrofluoric acid-containing solution, and dissolving porous layer by contacting with chemical dissolution solution
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Related Materials Visit the inventor's lab link at http://chem-faculty.ucsd.edu/sailor/research. Tech ID/UC Case 20633/2002-144-0 Related Cases 2002-144-0
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