A High-Throughput Asynchronous Pipeline Style Using a Transition-Signaling Protocol
Steven M. Nowick, Ph.D.
Reduces overhead communication of a high-speed synchronous clockAllows design of very high-throughput fine-grain pipeline circuits to the maximum extentAvoids explicit latches with a clocked-CMOS style to improve area and performanceUses simple, easily met, one-sided timing constraints for practical design that is easy to implementReduces pipeline cycle timePatent information:Patent Pending (WO/2002/035346)Tech Ventures Reference: IR M01-020
Wearable electronics such as watches, glasses, wristbands and athletic gearBiosensors with electronic interfacesTablet, laptop, computer microprocessorsLab on a chip technologyEthernet switch chipsLow-latency finite-impulse response filter chips
Steven M. Nowick, Ph.D.
美國
