Wire Width Planning for VLSI Interconnect Performance Optimization
This new system leads to optimal or near-optimal designs with greatly simplified routing architecture. Compared with other methods, it offers: Improved circuit performance due to automatic optimal wire width planning; Better control of performance and area trade-off given the method's flexibility in handling various optimization objectives; Shorter design time due to top-down planning and simplification of routing architecture; Better routing completion rate due to simplification of routing architecture.
This method can be used for circuit performance optimization and performance/cost trade-off in deep sub-micron integrated circuit designs. It can likely be generalized for crosstalk noise control and optimization.
Scientists at the University of California have developed a general and efficient method of wire width planning which can incorporate different factors, including design objectives and wire length distribution functions. This method can select a very small set of predetermined wire widths per metal layer, yet achieve near-optimal interconnect delay. Test results indicate only a 3-7% error while using just two widths, compared to complicated wire sizing and spacing algorithms, which use significantly more wire widths.
Patent Number: US6408427B1
Application Number: US2000510068A
Inventor: Cong, Jingsheng | Pan, Zhigang
Priority Date: 22 Feb 2000
Priority Number: US6408427B1
Application Date: 22 Feb 2000
Publication Date: 18 Jun 2002
IPC Current: G06F001750
US Class: 716129 | 716013 | 716134 | 716002
Assignee Applicant: The Regents of the University of California
Title: Wire width planning and performance optimization for VLSI interconnects
Usefulness: Wire width planning and performance optimization for VLSI interconnects
Summary: For planning wire width and optimizing performance for very large scale integration (VLSI) interconnect and also used for RTL planning interconnect-driven synthesis, floor planning and placement.
Novelty: Wire width planning and performance optimization method for very large scale integration interconnect, involves generating optimized layout for interconnect using set of globally optimal wire widths
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半导体
6408427
BACKGROUND Additional Technologies by these Inventors Tech ID/UC Case 10167/2000-134-0 Related Cases 2000-134-0
For deep sub-micron (DSM) designs, wiring delays have exceeded transistor delays and become the dominant factor in determining overall circuit performance. To achieve minimal wire delay, a number of techniques have been introduced that use continuous or discrete wire widths selectively in an interconnect structure. These techniques, however, tend to complicate the layout design considerably (especially for detailed routing) due to the use of many wire widths.
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